Non-Hanan Routing - Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

نویسندگان

  • Huibo Hou
  • Jiang Hu
  • Sachin S. Sapatnekar
چکیده

This work presents a Steiner tree construction procedure, Maximum delay violation Elmore routing tree, to meet specified sink arrival time constraints. It is shown that the optimal tree requires the use of non-Hanan points. The procedure works in two phases: a minimum-delay Steiner Elmore routing tree is first constructed using a minor variant of the Steiner Elmore routing tree procedure, after which the tree is iteratively modified, using an efficient search method, to reduce its length. The search method exploits the piecewise concavity of the delay function to arrive at a solution efficiently. Experimental results show that this procedure works particularly well for technologies where the interconnect resistance dominates, and significant cost savings are shown to be generated.

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

New Performance-Driven FPGA Routing Algorithms - Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Motivated by the goal of increasing the performance of FPGA-based designs, we propose new Steiner and arborescence FPGA routing algorithms. Our Steiner tree constructions significantly outperform the best known ones and have provably good performance bounds. Our arborescence heuristics produce routing solutions with optimal source–sink pathlengths, and with wirelength on par with the best exist...

متن کامل

SPAR: a schematic place and route system

This paper presents an approach to the automatic generation of schematic diagrams from circuit descriptions. The heuristics which make up the system are based on two principles of schematics readability: Functional Identi cation and Traceability. SPAR's generation process is broken into ve distinct phases: partitioning the netlist, placement of components on the page, global routing, local rout...

متن کامل

Planar Topological Routing - Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

We develop a simple linear time algorithm to determine if a collection of two-pin nets can be routed, topologically, in a plane (i.e., single layer). Experiments indicate that this algorithm is faster than the linear time algorithm of Marek-Sadowska and Tarng. Topological routability testing of a collection of multipin nets is shown to be equivalent to planarity testing, and a simple linear tim...

متن کامل

Machine Learning Attacks on PolyPUF, OB-PUF, RPUF, and PUF-FSM

A physically unclonable function (PUF) is a circuit of which the input– output behavior is designed to be sensitive to the random variations of its manufacturing process. This building block hence facilitates the authentication of any given device in a population of identically laid-out silicon chips, similar to the biometric authentication of a human. The focus and novelty of this work is the ...

متن کامل

COP: A Crosstalk OPtimizer for Gridded Channel Routing - Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

The interwire spacing in a VLSI chip becomes closer as the VLSI fabrication technology rapidly evolves. Accordingly, it becomes important to consider crosstalk caused by the coupling capacitance between adjacent wires in the layout design for the fast and safe VLSI circuits. The upper bounds of the allowable crosstalk for nets, called crosstalk constraints, are usually given in the design speci...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 1999